1. Field of the Invention
The present invention relates to a data-processing device and a data-processing method. This application claims priority from Japanese Patent Application No. 2011-066055, filed on Mar. 24, 2011, in the Japan Patent Office (JPO), the entire content of which is hereby incorporated by reference.
2. Description of the Related Art
An imaging apparatus, such as a still camera, a video camera, a medical endoscope camera, or an industrial endoscope camera, needs to process image data containing a large number of pixels (hereinafter referred to as “pixel data”) with the recent increase of pixel numbers and speed of the imaging apparatus. In such an imaging apparatus, a memory for temporarily storing data is used when each processing block in the imaging apparatus processes image data obtained by photographing. Image data in each processing step is temporarily stored in the memory.
FIG. 19 is a block diagram showing a schematic configuration of a conventional imaging apparatus. For example, image data processing in a photographing operation of the imaging apparatus shown in FIG. 19 is performed in the following order.
(Step 1): First, an imaging-processing unit, for example, transmits image data obtained by a CCD (Charge-Coupled Device) solid-state imaging device to a memory via an output DMA (Direct Memory Access) unit to temporarily store the image data.
(Step 2): Subsequently, an image-processing unit reads the image data temporarily stored in the memory via an input DMA unit. The image-processing unit performs image processing for recording or display of the read image data. The image-processing unit then transmits the processed image data to the memory via the output DMA unit to temporarily store the image data.
(Step 3): Subsequently, a display-processing unit reads the image data subjected to image processing for display via an input DMA unit and causes a display device to display the image data.
Thus, in the imaging apparatus, the preceding processing block temporarily stores the image data in the memory. The subsequent processing block reads the image data stored in the memory and performs a next process. Thus, as respective processing blocks in the imaging apparatus perform delivery of the image data, which is a processing target, through the memory, processes of the imaging apparatus are sequentially performed.
In recent years, it has been preferable for an imaging apparatus such as a still camera, a video camera or the like to be able to be continuously used for a long time. Accordingly, there is a need for a technique for reducing power consumption of an electrical circuit of the imaging apparatus. One method of reducing the power consumption of the imaging apparatus includes a method of increasing a transfer rate for image data between each processing block (electrical circuit) and a memory. The increase of the transfer rate for image data, for example, may be realized by increasing a frequency of an operation clock of the imaging apparatus or shortening a transfer period of time of the image data between the processing block and the memory. These methods reduce power consumption due to transfer of the image data by increasing the transfer rate of the image data.
As a technique for shortening a transfer period of time of image data between the processing block and the memory, a packing technique as disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 is known. The packing technique disclosed in Japanese Patent Laid-Open Publication No. 2007-312358 is a technique of extending a bus width of a data bus used when each pixel data in the image data is transferred to a memory and arranging (packing) a plurality of adjacent pixel data in the data bus to transfer a plurality of pixel data at a time. Using this technique, the number of data transfers required to transfer all pixel data can be further reduced over conventional data transfer in which pixel data is transferred pixel by pixel, and the period of time for data transfer of the image data can be shortened. For example, when pixel data obtained from a 16×16 Bayer arrangement CCD is transferred to a memory as shown in FIG. 20, in the packing technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, pixel data for 4 pixels is one transfer unit to transfer the pixel at a time, thus reducing a transfer period of the image data to ¼. Accordingly, it is possible to reduce power consumption of an electrical circuit in the imaging apparatus, unlike a case in which pixel data is transferred to the memory pixel by pixel.
As a technique of further shortening the transfer period of image data, a packing method using burst transfer of DMA is considered. This is a method in which one burst, which is a unit for accessing memory at a prescribed certain number of cycles, is considered a unit packing pixel data. FIGS. 21A and 21B show an example of pixel data packing. FIG. 21A illustrates the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358. An example in which the pixel data shown in FIG. 20 is packed is shown in FIG. 21A. FIG. 21B shows an example in which the pixel data shown in FIG. 20 is packed in a burst unit. An example in which a bus width (hereinafter referred to as “memory bus width”) of a data bus used when the pixel data is transferred to the memory (hereinafter referred to as “memory bus”) is 32 bits, and memory access for one cycle in burst transfer (hereinafter referred to as “one transfer”) is performed four times, that is, one burst transfer is performed through four transfers, is shown in FIGS. 21A and 21B. An example in which resolution of pixel data of one pixel, that is, a bit number of the pixel data, is 9, 10, 12, and 14 from top to bottom, is shown in FIGS. 21A and 21B.
As can be seen from FIGS. 21A and 21B, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 shown in FIG. 21A, pixel data for two pixels per one transfer can be arranged on a memory bus, and pixel data for 8 pixels per one burst can be transferred to the memory. On the other hand, in the burst unit-based packing method shown in FIG. 21B, pixel data for 14, 12, 10, and 9 pixels can be transferred to the memory. In the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, since pixel data is arranged (packed) in the memory bus width, that is, in a unit of one transfer, a sum of bit numbers of a plurality of arranged pixel data must not exceed the memory bus width. Accordingly, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, there are many bits to which pixel data cannot be allocated (hereinafter referred to as “unused bits”) within the memory bus width. On the other hand, in the burst unit-based packing method, since pixel data is arranged (packed) in units of bursts, even when a sum of bit numbers of a plurality of arranged pixel data exceeds the memory bus width, the pixel data can be arranged (packed) in a next transfer as long as the sum does not exceed one burst, as in FIG. 21B. That is, in the burst unit-based packing method, even when the memory bus width is not an integer times the resolution of pixel data, the pixel data can be arranged (mapped) over one transfer unit, which can reduce the number of unused bits. Accordingly, in the burst unit-based packing method, much pixel data can be transferred to the memory in the same time, that is, the transfer period of time of the image data can be shortened, and the power consumption of the electrical circuit in the imaging apparatus can be further reduced over the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358.
In general, when data change (change (inversion) of data “0”→“1” or “1”→“0”) is less, power consumption is known to be lower. Accordingly, reducing the power consumption of the imaging apparatus by reducing the data change on the memory bus between each processing block (electrical circuit) and a memory in the imaging apparatus is also considered. FIGS. 22A, 22B, 22C and 22D are diagrams illustrating a relationship between the data change on the data bus (memory bus) between the processing block and the memory in the imaging apparatus and the power consumption. FIG. 22A shows an example in which a bus width of a memory bus between the imaging-processing unit and the memory in the imaging apparatus shown in FIG. 19 is 32 bits. The data change on the memory bus is schematically shown in FIGS. 22B to 22D. In the example of FIGS. 22A to 22D, power consumption is lowest in the case of FIG. 22B in which there is no data change on the memory bus, and highest in the case of FIG. 22D in which there is the most data change on the memory bus.
From the above, if there is a great amount of change in pixel data between two continuous transfers (e.g., pixel data in first and second transfers of each burst transfer shown in FIG. 21B) in the burst transfer between each processing block and the memory in the imaging apparatus, power consumption due to the transfer of the image data increases. That is, the power consumption due to the transfer of the image data varies in proportion to the number of the same bits (bit number) on the memory bus that have changed between the two transfers.
In general, there is expected to be a small amount of change in data between adjacent pixels in image data, and bits whose values are being inverted are expected to be fewer than bits whose values are not being inverted when the same bits of pixel data of adjacent pixels are compared. Here, when the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, which is shown in FIG. 21A, and the burst unit-based packing method, which is shown in FIG. 21B, are compared with each other, the power consumption due to the transfer of the image data is lower in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 in which the same bits are aligned in pixel data with the same colors, as shown in FIGS. 23A and 23B. Further, FIGS. 23A and 23B show a case in which the bit number of pixel data of one pixel is 9 in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, which is shown in FIG. 21A, and the burst unit-based packing method shown in FIGS. 21B.
More specifically, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 shown in FIG. 23A, least significant bits of the memory bus shown in a range A are all the same bits (least significant bits) of pixel data with the same colors. On the other hand, in the burst unit-based packing method shown in FIG. 23B, least significant bits of the memory bus shown in a range B are all different bits of pixel data having different colors. It can be seen from this that, when locations of bits of pixel data arranged on the memory bus are made different between two continuous transfers by packing the image data in a burst unit, a change amount of the same bits on the memory bus becomes great and the power consumption due to the transfer of the image data increases.
That is, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 shown in FIG. 23A, the power consumption due to the transfer of the image data is low, but data transfer efficiency is low. In the burst unit-based packing method shown in FIG. 23B, the data transfer efficiency is good, but the power consumption due to the transfer of the image data is high.
Further, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, for example, pixel data of three pixels can be arranged (packed) in one transfer in which the pixel data is packed, as shown in FIG. 24. However, in this case, for example, least significant bits of the memory bus shown in a range C are the same bits (least significant bits) of the pixel data, but with different colors. The pixel data having different colors is highly likely to be greatly different in value, and even in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, the power consumption due to the transfer of the image data may be not reduced by the pixel data arrangement in one transfer.